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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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Programmable CMOS PLL high-frequency divider
The divider consists of the input signal preamplifier (buffer), the converter of a differential input signal to an unipolar signal with a supply voltage peak-to-peak, the prescaler with variable dividing ratio 4/5 and the programmable divider on the basis on two binary decade counters.
The block is fabricated on TSMC BiCMOS 0.18 um.
The block is fabricated on TSMC BiCMOS 0.18 um.
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