Pulse Per Second (PPS) Clock to PPS core

NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configurable frequency, it is intended to be connected to a PPS Slave core able to syntonize to a Pulse per Second. The core also checks if the input clock is in the configured range and only if so will generate a PPS. The core can be configured either by signals or by an AXI4Lite-Slave Register interface.

This core is intended to be used with either external clocks or also SyncE clocks when the frequency shall be adjusted numerically rather than a clock switch.

• see the entire Pulse Per Second (PPS) Clock to PPS core datasheet
• get in contact with Pulse Per Second (PPS) Clock to PPS core Supplier