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QOI Lossless Image Decompression Core
The QOID Core is a decoder that implements a highly-efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format (QOI) specification, version 1.0.
The QOI algorithm compresses RGB or RGBA images with 8 bits per color without any loss. It has a compression efficiency close to that of the PNG compression, at a fraction of the computational complexity.
Capitalizing on the simplicity of the QOI algorithm, the QOID encoder core can decompress images at a very high speed and with minimal silicon resources. The core occupies approximately 15,000 equivalent NAND2 gates and can process one pixel per clock cycle. A single core instance can compress images at rates sufficient for UHD 4k30 video even in low-end FPGAs, 4k60 in mid-range FPGAs, and 8k30 or 60 in modern ASIC technologies.
The core is designed for ease of use and integration and adheres to coding and verification best practices. It requires no assistance from a host processor and uses simple handshake interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.
The QOI algorithm compresses RGB or RGBA images with 8 bits per color without any loss. It has a compression efficiency close to that of the PNG compression, at a fraction of the computational complexity.
Capitalizing on the simplicity of the QOI algorithm, the QOID encoder core can decompress images at a very high speed and with minimal silicon resources. The core occupies approximately 15,000 equivalent NAND2 gates and can process one pixel per clock cycle. A single core instance can compress images at rates sufficient for UHD 4k30 video even in low-end FPGAs, 4k60 in mid-range FPGAs, and 8k30 or 60 in modern ASIC technologies.
The core is designed for ease of use and integration and adheres to coding and verification best practices. It requires no assistance from a host processor and uses simple handshake interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.
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Block Diagram of the QOI Lossless Image Decompression Core IP Core
