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QSGMII/SGMII/1000BASE-X and MAC
The fully integrated 5G QSGMII, 2.5G/1.25G SGMII and 1000BASE-X Physical Coding Sublayer (PCS-X) and Media Access Controller (MAC) core for Ethernet applications is complaint with IEEE 802.3 standard and QSGMII and SGMII specifications. The interface to the PMA supports a single channel Tri mode bi-directional, serial interface. The PCS sublayer supports 8B10B encoding (QSGMII/SGMII/1000BASE-X). This Tri-Mode Core is configurable through software register.
The West-bound interface from the MAC provides a configurable 32-bit system interface.
The East-bound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES.
The West-bound interface from the MAC provides a configurable 32-bit system interface.
The East-bound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES.
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Block Diagram of the QSGMII/SGMII/1000BASE-X and MAC IP Core
QSGMII IP
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more
- MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
- QSGMII
- Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
- Networking SerDes IP, Silicon Proven in ST 28FDSOI