QUAD SPI Memory controller

The core maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. Reading memory is performed by directly accessing the memory using reads on a AHB slave interface. Other operations, e.g. writes, are performed by sending SPI commands using the core's register interface. The SPIMCTRL supports most SPI Flash devices.
The SPIMCTRL can be configured to support a wide range of SPI instruction types/protocols through the Quadinput, Dualinput, Quadoutput, Dualoutput, DSPI and QSPI bits.

The SPIMCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies.

The SPIMCTRL core can be licensed under the GPL or a commercial license as part of the GRLIB IP library.

• see the entire QUAD SPI Memory controller datasheet
• get in contact with QUAD SPI Memory controller Supplier