RAM-based Shift Register

The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in Xilinx FPGA devices. Implementing Shift Registers with the SRL16/SRL32 provides large resource and power savings. The IP supports fixed-length or variable-length shift registers.

• see the entire RAM-based Shift Register datasheet
• get in contact with RAM-based Shift Register Supplier