RapidIO PHY

RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors and communications. RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications which includes Logical, Common Transport and Physical layers, in which the Physical layer defines the interface between two devices and the packet transport mechanism, flow control and electrical characteristics.
KNiulink RapidIO PHY offers the physical layer specification solution as defined in the RapidIO Specification Rev 4.0/3.1/2.2. The IP supports four-lane running at different transmission speeds up to 6.25/ 10.3125/25.78125Gbps.

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