RapidIO to AXI Bridge

The RapidIO to AXI Bridge is a highly flexible and configurable IP used along with the native RapidIO Controller (GRIO) to provide RapidIO interface on one side and AXI interface on the system side. The Bridge has been architectured to interface with a RapidIO controller used as a Host or device. The RIO-AXI BRIDGE uses high speed multi-channel DMA and Message controllers to match the bandwidth requirements of the RIO solution.

The RapidIO to AXI Bridge is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The RapidIO to AXI Bridge provides highly scalable bandwidth through a configurable data path width and clock frequency.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.

• see the entire RapidIO to AXI Bridge (RAB) datasheet
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