USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
Register File with low power retention mode, high speed pins on 1 side
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Single port register file IP
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
- Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
- Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits