MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode
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Block Diagram of the Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode
Combo Regulators IP
- TSMC 22ULL Combo voltage regulator combining a linear regulator for active mode with an ultra-low quiescent regulator for sleep mode
- TSMC 40 ULP eFlash Combo voltage regulator combining a linear regulator for active mode with an ultra-low quiescent regulator for sleep mode
- TSMC 40nm LP combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
- TSMC 40 ULP Combo voltage regulator combining a linear regulator for active mode with an ultra-low quiescent regulator for sleep mode
- GF 22FDX combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
- TSMC 40nm ULP combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode