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RISC-V-based SoC template
IOb-SoC is a RISC-V SoC that can be configured in Python and generated in Verilog, The core is open-source and can be downloaded from https://github.com/IObundle/iob-soc
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Block Diagram of the RISC-V-based SoC template IP Core
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core