RISC-V Secure Enclave IP

The TESIC-510 Secure Enclave IP provides the highest levels of security for an SoC. Based on a secured RISC-V RV32IMCB processor core the Secure Enclave includes patented design techniques and countermeasures against side channel and perturbation attacks.

The standardised RISC-V architecture facilitates software development, supported by certified cryptographic libraries and utility functions.

Cryptographic hardware accelerators provide efficient support for standard cryptography and security operations increasing throughput while respecting power constraints and security requirements.

The BootROM and secondary boot loader firmware manage the certified life cycle and enforce and assure security from manufacturing to deployment.

• see the entire RISC-V Secure Enclave IP datasheet
• get in contact with RISC-V Secure Enclave IP Supplier