RSA IP Core
RSA IP cores consist of a cluster of IPs. VHDL is used as the Hardware Description Language of the IP Cores. The cluster includes ADDSUB (Addition and substruction), MULT (Multiplication), BAR_DIV (Barrett Divider), MOD_INV (Modulo Inversion) and MME (Montgomery Modulo Exponentiation) IP Cores. MME cores are configurable, and their number can be changed.
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Block Diagram of the RSA IP Core IP Core

RSA IP
- Secure-IC Securyzr™ Tunable Cryptography solutions with embedded side-channel protections: AES - SHA2 - SHA3 - PKC - RSA - ECC - ML-KEM - ML-DSA - XMSS - LMS - SM2 - SM3 - SM4 - Whirlpool - CHACHA20 - Poly1305
- Secure-IC's Securyzr™ Tunable Public Key Cryptographic (RSA, ECDSA, SM2, Diffie-Hellman) accelerator - optional SCA protection
- RSA Keygen IP Core
- Java Card compliant cryptographic library for encryption and decryption of RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Secure cryptographic library compliant with the X9.31 and FIPS 186-4 standards.