Samsung 28nm FDSOI 1.8v/1.0v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] and DN [11:0] to different values according to different REFIN, CLK_VCO will be locked at the multiples of input frequency.CLKO is CLK_VCO divided by DP[2:0].

• see the entire Samsung 28nm FDSOI 1.8v/1.0v APLL datasheet
• get in contact with Samsung 28nm FDSOI 1.8v/1.0v APLL Supplier