MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
SC12 Standard Cell Library - IBM 65 nm CMOS10SF
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Logic IP IP
- H.264 Baseline Encoder with compressed reference frame store
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
- Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)