Bluetooth Dual Mode v5.4 / IEEE 15.4 PHY/RF IP in TSMC22nm ULP
SC9 Standard Cell Library - GLOBALFOUNDRIES 130 nm CH013LPHV
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Logic IP IP
- Aeonic Generate Digital PLL for multi-instance, core logic clocking
- H.264 Baseline Encoder with compressed reference frame store
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)