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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
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Scalable 3D Graphics Accelerator
The logi3D graphics accelerator IP core is specifically designed for the new Xilinx Zynq-7000 All Programmable SoC. Designers can add attractive 3D graphics, including advanced Graphical User Interfaces (GUI), to their Xilinx Zynq-7000 AP SoC design by combining the logi3D with their application specific IP cores in a plug-and-play manner. The IP core is designed to support the OpenGL ES 1.1. API*. Linux and Windows Embedded Compact 7 are the currently supported operating system, with support for Android planned for 4Q2012. Due to its AMBA AXI4 interface compliance the logi3D IP core can also be implemented on Xilinx 7 Series and other Xilinx FPGA families as a Graphics Processing Unit (GPU) in various ASSP plus FPGA combinations.
* Product is based on a published Khronos specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
* Product is based on a published Khronos specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
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Video Demo of the Scalable 3D Graphics Accelerator IP Core
3D graphics demos rendered by Xylon's logi3D Scalable 3D Graphics Accelerator IP core running on the Xilinx® ZC702 Evaluation Board. The logi3D is designed to support the OpenGL® ES 1.1 API and run on the Xilinx Zynq™-7000 EPP. Due to its ARM® AMBA® AXI4 compliance, the logi3D IP core can also be used with the Xilinx 7 Series and other FPGA families.