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SD 4.1 SDIO 4.1 Host Controller IP
The SD4.0/SDIO4.0/eMMC5.0 Host Controller IP is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
- SD4.0
- SDIO4.0
- eMMC5.0
This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The SD4 / eMMC5.0 host interface is based on a standard 32-bit AXI bus which is used to transfer data and configure the IP.
- SD4.0
- SDIO4.0
- eMMC5.0
This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The SD4 / eMMC5.0 host interface is based on a standard 32-bit AXI bus which is used to transfer data and configure the IP.
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Block Diagram of the SD 4.1 SDIO 4.1 Host Controller IP IP Core
