English
You are here:
Serial Peripheral Interface
CoreSPI implements SPI and can operate as either a Master or a Slave. When operating in Master mode, the core generates the serial data clock (m_sck) and selects the Slave device that will be accessed. When operating in Slave mode, another Master device generates s_sck and activates the Slave select input of the core in order to communicate.
Description: CoreSPI Serial Peripheral Interface
* A point to point serial interface
* Popular for low-cost, low-speed "in-box" communication
* Available as a master and/or slave
* Full duplex, synchronous, 8-bit serial data transferHigh bit rates
* 8 slave select lines
* MSB- or LSB-first data transfer
Description: CoreSPI Serial Peripheral Interface
* A point to point serial interface
* Popular for low-cost, low-speed "in-box" communication
* Available as a master and/or slave
* Full duplex, synchronous, 8-bit serial data transferHigh bit rates
* 8 slave select lines
* MSB- or LSB-first data transfer
View Serial Peripheral Interface full description to...
- see the entire Serial Peripheral Interface datasheet
- get in contact with Serial Peripheral Interface Supplier
Serial Peripheral Interface IP
- Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- SPI Serial Peripheral Interface Master/Slave
- SPI Serial Peripheral Interface Master/Slave
- Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
- Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support