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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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SerialLite PHY with PCS
The VSG1G55SL2 is an enhanced High-Speed SerialLite macro with data transfer capabilities of up-to 3.125Gbps. It includes the PCS layer within the Macro and is capable of directly interfacing with the ASIC core. In addition, on the same footprint using Gigacom's technology, it includes a standard JTAG interface, Scan interface and a Serial interface.
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Block Diagram of the SerialLite PHY with PCS IP Core
