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SGMII PHY
The Innosilicon SGMII PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 1000BASEX specification.
This document describes the operation and performance of the PHY and describes how to program the PHY to support different standards and testing modes using Innosilicon’s PHY Programming Utility. The PHY module includes a top-level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
This document describes the operation and performance of the PHY and describes how to program the PHY to support different standards and testing modes using Innosilicon’s PHY Programming Utility. The PHY module includes a top-level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.
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SGMII IP
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
- 32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- 32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- 25GE/10GE/SGMII/1000BASE-X and MAC