Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process

TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock & data recovery, Serialization and De-Serialization of Data, 128/132b data coding, Receiver detection.

TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 65nm GP process.

* A limited number of Test Chips manufactured in TSMC 65GP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.

• see the entire Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process datasheet
• get in contact with Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process Supplier