Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process

TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features like clocking and clock & Data recovering, Serialization and De-Sterilization of Data, 128/130b, data coding, Receiver detection.

TERMINUS-CIRCUITS’s PCIe GEN 3.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 3.0 PHY IP is available in GF 28nm SLP process.

* A limited number of Test Chips manufactured in GF 28SLP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.

• see the entire Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process datasheet
• get in contact with Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process Supplier