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10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
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Single port SRAM Compiler - low power retention mode and column repair
Single Port SRAM Compiler with Low Power Retention Mode and Ultra Low Leakage
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low power retention mode IP
- Register File with low power retention mode and 3 speed options
- Single port SRAM Compiler - low power retention mode
- Single port SRAM Compiler - low power retention mode
- Register File with low power retention mode, high speed pins on 1 side
- Two port register file (1R1W) with low power retention mode
- Single Port SRAM with low power retention mode, high speed pins on 1 side