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Slave HSSL Controller
The logiHSSL IP core enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%.
The new IP core allows system designers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL. The logiHSSL IP is prepared for the Xilinx Vivado Design Suite to enable quick and efficient resource implementations in the latest Xilinx All Programmable devices for use in the embedded systems that meet the highest safety standards.
The new IP core allows system designers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL. The logiHSSL IP is prepared for the Xilinx Vivado Design Suite to enable quick and efficient resource implementations in the latest Xilinx All Programmable devices for use in the embedded systems that meet the highest safety standards.
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