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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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Slave I2C bus controller with FIFO
The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as:
- a slave transmitter or
- slave receiver
depending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:
- clock synchronization,
- arbitration,
- high-speed transmission mode.
The DI2CS supports all transmission speed modes:
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
DCD’s IP Core is a technology independent design and can be implemented in various process technologies.
- a slave transmitter or
- slave receiver
depending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:
- clock synchronization,
- arbitration,
- high-speed transmission mode.
The DI2CS supports all transmission speed modes:
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
DCD’s IP Core is a technology independent design and can be implemented in various process technologies.
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