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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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SM4 Crypto Accelerator
The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for fast integration, low gate count, and maximum performance, the SM4 Engine provides a reliable and cost-effective SM4 IP solution that is easy to integrate into SoC designs.
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SM4 IP
- Secure-IC Securyzr™ Tunable Cryptography solutions with embedded side-channel protections: AES - SHA2 - SHA3 - PKC - RSA - ECC - Crystals Kyber - Crystals Dilithium - XMSS - LMS - SM2 - SM3 - SM4 - Whirlpool - CHACHA20 - Poly1305
- Secure-IC's Securyzr™ Tunable SM4 Hardware accelerator with SCA protections
- Secure-IC's Securyzr(TM) SM4 Crypto Engine
- Security Protocol Accelerator for SM3 and SM4
- SM4 Encoder and Decoder
- Secure-IC's Securyzr™ SM4-GCM Multi-Booster