SMBus IO Pad Set

The SMBus library provides open-drain bi-directional I/O cells designed for the High-Power SMBus two-line interface. It is compliant with the Rev 3.1 of the SMBus specification.
The design supports the Sm, Fm and Fm+ modes of operation at the SMBus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.

This 7nm library is available in a staggered flip chip implementation.

To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the SMBus cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

ESD Protection:
▪ JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)

Latch-up Immunity:
▪ JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C

• see the entire SMBus IO Pad Set datasheet
• get in contact with SMBus IO Pad Set Supplier