The present IP is a VCC Detector (VDT) circuit which detects the voltage level of its power supply, AV18. The normal operation voltage range of AV18 is 1.62v~1.98v. When the detected voltage AV18 increases beyond the detection level VR18, the corresponding output OUTP15 is generated as a high level logic. When the detected voltage AV18 decreases below the detection level VF18, the corresponding output OUTP15 is generated as a low level logic. This system consists of one comparator sub-circuit and needs an external bandgap which can be provided by the VeriSilicon IP, SMIC18_PRG_03E. The output may be at the wrong voltage level during the power-up stage before the bandgap becomes stable.