SMIC 55nm LL USB2.0 PHY

Features

• Compliant with the USB Spec Rev2.0
• Compliant with the UTMI Spec Rev1.05
• Compliant with the UTMI+ Spec Rev1.0 Level3
• Supports 480Mbit/s “High Speed”, 12Mbit/s “Full Speed” and 1.5Mbit/s “Low Speed”
• Supports 60MHz/8-bit interface and 30MHz/16-bit interface
• 12MHz/24MHz external crystal, internal oscillator and PLL are used for generating high-speed internal clock and CLKOUT output
• Internal terminations include 1.5Kohm pull-up resistor switching on DP/DM in the FS mode and the HS chirp mode
• Clock and data recovery from serial stream on the USB bus
• Supports detection of USB reset, suspend, resume and remote-wake-up features
• Supports the test modes defined in the USB2.0 Specification
• NRZI and Bit Stuff encoding and decoding
• Supports low/full speed serial mode
• Works as host PHY or device PHY by setting DPPULLDOWN and DMPULLDOWN
• Process:SMIC 55nm Low Leakage process
• Supply voltage: 1.08v~1.2v~1.32v, 2.25v~2.5v~2.75v, 2.97v~3.3v~3.63v
• Operating junction temperature: - 40°C ~ +25°C ~ +125°C
• More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp