SMIC 65nm LL 1.2v/2.5v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 300MHz to 900MHz. By setting DM [3:0] and DN [6:0] to different values according to different CLKIN, CLK will be locked at the multiples of input frequency.

• see the entire SMIC 65nm LL 1.2v/2.5v APLL datasheet
• get in contact with SMIC 65nm LL 1.2v/2.5v APLL Supplier