Soft SDRAM Controller for AXI Interface

CoreSDR_AXI is intended to provide a 64-bit advanced microcontroller bus architecture (AMBA®) advanced extensible interface (AXI) to an external single data rate (SDR) synchronous dynamic random access memory (SDRAM). The design consists of an AXI controller, read and write data buffers, and a single instantiation of CoreSDR, which contains a generic CPU interface.

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