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SPDIF IP
The SmartDV SPDIF IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The SPDIF IIP can be implemented in any technology. The SPDIF IIP core supports the SPDIF 2.2A standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Tilelink or custom buses.
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SPDIF IP IP
- SPDIF-Rx-Pro : Configurable SPDIF-AES/EBU Receiver
- SPDIF-Tx-Pro : Configurable SPDIF/AES3 Transmitter
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- SPDIF
- MPEG-1/2 – Layer I/II Audio Decoder
- Dolby Digital/AC-3/MPEG Audio Decoding Core