Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process

UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.

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Library IP

DP/eDP1.4b RX PHY
DP/eDP1.4b TX PHY
DesignWare Library contains the essential infrastructure IP for design and verification
Library of mathematical and floating point (FP) components
MIPI D-PHY TX
Standard Cell Library in TSMC (12nm~180nm)

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