Standard digital, analog and oscillator IO
Features
- Standard digital, analog and oscillator IO
- Cell Size (Width * height) 30um * 155um with DUP stagger bonding pads
- Work voltage: 1.8V~3.3V power
- Robust whole chip multi-domain ESD solution with competitive cell size
- SMIC 0.040um Logic Salicide 1.1V/2.5V low leakage Process
- Suitable for 7, 8 and 9 layers application (single top metal)
- Suitable for 7, 8, 9 and 10 layers application (double top metal)
View Standard digital, analog and oscillator IO full description to...
- see the entire Standard digital, analog and oscillator IO datasheet
- get in contact with Standard digital, analog and oscillator IO Supplier
IO IP
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- TSMC 3nm (N3E) 1.8V SD/eMMC IO
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF