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Streaming Multi-port SDRAM Memory Controller IP Core

The Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory. The core integrates: a burst memory controller core, a port arbitrator and intelligent look-ahead FIFO controller into one easy-to-use core. It supports SDR, DDR, DDR2 and Mobile DDR memory devices in a single IP Core assuring designers of a smooth low-risk migration path with changing SDRAM technology.

The Streaming Multi-port SDRAM Memory Controller IP Core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system.

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Block Diagram of the Streaming Multi-port SDRAM Memory Controller IP Core

Streaming Multi-port SDRAM Memory Controller Block Diagam

Multi-port IP

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Streaming Multi-port SDRAM Memory Controller IP Core

View Streaming Multi-port SDRAM Memory Controller full description to...

Block Diagram of the Streaming Multi-port SDRAM Memory Controller IP Core

Multi-port IP

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