Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component

Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo may find use where there is the need for a high-resolution, modest-accuracy timebase. TimeServo’s PI-DPLL allows a local TCXO to be disciplined by an external 1 PPS signal to achieve excellent syntonicity. In conjunction with timestamp-capable MACs (not included) and host-control software (as-is examples provided), TimeServo is a vital and central component of an IEEE-1588/PTP system.

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