MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3
View Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 full description to...
- see the entire Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 datasheet
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IO IP
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- TSMC 3nm (N3E) 1.8V SD/eMMC IO
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF