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Synthesized RTL of SRAM/NOR memory controller with ECC IP-core (AXI interface)
Features
- • Configurable timing parameters exchange with SRAM- NOR-memory;
- • Configurable to support up to 6 banks of memory;
- • Configurable to support up to 26 bit address;
- • 32-bit data bus;
- • System interface - AXI 3.0 or MCIF II;
- • APB 3.0 interface for configuration;
- • Support ECC (error-correcting code - corrects a single error and detects double errors on a 32-bit data).
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