Tessent AI IC debug and optimization

The multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications provide unique challenges for development, verification, and validation teams. The larger number of cores that are directly programmable plus the data bandwidth and process synchronization issues designers need to deal with add up to an embedded system that is increasingly difficult to validate and optimize.

Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs. Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, debug and software engineers can observe what’s happening in the design when operational software is running on the system. The instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.

All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.

• see the entire Tessent AI IC debug and optimization datasheet
• get in contact with Tessent AI IC debug and optimization Supplier