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Tessent Bus Monitor
The Tessent Embedded Analytics Bus Monitor provides non-intrusive monitoring of interconnect activity across all major standards, including Arm® AMBA® AXI, ACE, and ACE-lite.
The Bus Monitor enables full transaction-level visibility of traffic buses with a wide range of measurements, analytics and statistics gathering. All of these are run-time configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The modules can track transactions (e.g. trace) and automatically gather statistics to identify issues such as contention, peak traffic, and deadlock.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
The Bus Monitor enables full transaction-level visibility of traffic buses with a wide range of measurements, analytics and statistics gathering. All of these are run-time configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. The modules can track transactions (e.g. trace) and automatically gather statistics to identify issues such as contention, peak traffic, and deadlock.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
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Block Diagram of the Tessent Bus Monitor IP Core
