TSMC CLN65GP 65nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

• see the entire TSMC CLN65GP 65nm Deskew PLL - 130MHz-650MHz datasheet
• get in contact with TSMC CLN65GP 65nm Deskew PLL - 130MHz-650MHz Supplier