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TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP detailed functional information, please refer to IP datasheet for IGAD2DX01A. This test chip adopts TSMC CLN6FF
Process: TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process or
TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
This test chip adopts TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
Layer & Device: High R Resistance, ULVT
Metal Scheme: 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R) or
1P13M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Z)
This test chip adopts 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R)
Process: TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process or
TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
This test chip adopts TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
Layer & Device: High R Resistance, ULVT
Metal Scheme: 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R) or
1P13M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Z)
This test chip adopts 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R)
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