TX & RX FIR Filter specifically to support DSP Application

Features

• Synthesizable, technology-independent IP Core for FPGA/ASIC and SoC
• Coded with Verilog
• It support 2 type of filters, Equiripple and Root Rise Cosine (RRC)
• 16/12-bit Fixed-Point Representation/Operation (Imaginary and Real Number)
• Parameterizable variables of filter orders, filter coefficients, fixed-point quantization bits of filter coefficients and oversampling rates
• It could implemented with a maximum of 40 filter orders

Block Diagram of the TX & RX FIR Filter specifically to support DSP Application