MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
ULP 32.768kHz oscillator in Silterra 0.18 μm
A 6-bit digital bus allows frequency adjustment against process variations. It has self-biased, built-in references and doesn’t require external ones. The core is easily retargeted to any other CMOS technology due to its MOSFET-only oscillator architecture.
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Clock Management IP
- Controller IP, System Power/Clock Management, Soft IP
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