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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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Ultra High Density 6-track Standard Cell library - TSMC 55nm 55LP / LP_eF / ULP / ULP_eF / GP, supports 60/65/70nm channel length
Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable cells are available, and each one has been optimized for speed, routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost.
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standard cell library libraries IP
- Standard Cell Library in TSMC (12nm~180nm)
- SMIC 110nm Mixed Signal UHD RVT Process_x000D_ Standard Cell Library.
- SMIC 110nm Mixed Signal UHD HVT Process_x000D_ Standard Cell Library.
- SMIC 110nm Mixed Signal UHD LVT Process_x000D_ Standard Cell Library.
- SMIC 110nm Mix-signal (Rvt) high density standard cell library.
- SMIC 0.13um Low Leakage UHD RVT_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.