7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Ultra-low jitter, type-I ADDLL with adaptive dither cancellation-3GHz-5GHz
With an ultra-compact footprint (0.008 sq mm), it is particularly suited for SoC designs that require precise phase synchronization across multiple clock domains. The delay resolution is as fine as 700 fs. Thanks to its adaptive dithering cancellation technique, it mitigates dithering issues, significantly enhancing jitter performance.
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Block Diagram of the Ultra-low jitter, type-I ADDLL with adaptive dither cancellation-3GHz-5GHz
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