DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
Ultra-Low-Latency (ULL) Exact Match Search Engine
EMSE can be used either as a stand-alone FPGA IP using the hardware command interface or with an API so that data can be shared between software and logic on FPGA.
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Block Diagram of the Ultra-Low-Latency (ULL) Exact Match Search Engine
