Ultra-low-power AI/ML processor and accelerator

CSEM’s Fibonacci machine-learning (ML) accelerators are built on the principle of hierarchical scalability. Similar to the Fibonacci sequence, where each number is the sum of the two preceding ones, CSEM’s System on Chip (SoC) can dynamically enhance its computational power by adding accelerator resources as needed. This heterogeneous architecture includes a low-power time-series ML accelerator (FETA), two clusters of highly parallelized neural processing units (NPUs), energy-efficient on-chip memories, a versatile RISC-V microcontroller core, and a comprehensive set of peripherals for seamless system integration. Trained models can be deployed using CSEM’s ML compiler, which supports all common formats, such as ONNX.

NPU Clusters:

• Optimized for spatial neural networks (e.g. CNNs, ResNets, MobileNets)
• Sparsity exploitation
• Peak MAC performance: 160 GOPS

FETA Cluster:

• Optimized for temporal neural networks (e.g. RNNs like LSTM or GRU)
• Smart temporal feature extraction engine

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