Ultra Low-power, compact Hybrid Viterbi Decoder

This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 ACS units. The configurations with 1, 2, 4, 8 and 16 ACS units decode a message bit in 33, 17, 9, 5 and 3 clock cycles respectively. By implementing a register exchange traceback algorithm this core is suitable for applications with strict latency constraints. In particular the latency is equal to the traceback length. The regsiter exchange algorithm doesn’t require any RAM memory for storage.
The core can be used for streaming or packetised data applications. By using signed LLR input data it naturally supports de-puncturing by inserting zeros. The core provides automatic normalization of the path metrics, ensuring that overflow cannot occur.

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